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ltc3850 1 3850f typical application features applications description dual, 2-phase synchronous step-down switching controller the ltc ? 3850 is a high performance dual synchronous step-down switching regulator controller that drives all n-channel power mosfet stages. a constant-frequency current mode architecture allows a phase-lockable fre- quency of up to 780khz. power loss and supply noise are minimized by operating the two controller output stages out of phase. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the ltc3850 features a precision 0.8v reference and a power good output indicator. a wide 4v to 24v (28v maximum) input supply range encompasses most battery chemistries and intermediate bus voltages. independent tk/ss pins for each controller ramp the output voltages during start-up. current foldback limits mosfet heat dissipation during short-circuit condi- tions.the mode/pllin pin selects among burst mode ? operation, pulse-skipping mode, or continuous inductor current mode and allows the ic to be synchronized to an external clock. the ltc3850 is available in both low pro? le 28-pin 4mm 4mm qfn and narrow ssop packages. high ef? ciency dual 3.3v/2.5v step-down converter dual, 180 phased controllers reduce required input capacitance and power supply induced noise high ef? ciency: up to 95% r sense or dcr current sensing 1% 0.8v output voltage accuracy phase-lockable fixed frequency 250khz to 780khz supports pre-biased output dual n-channel mosfet synchronous drive wide v in range: 4v to 24v operation adjustable soft-start current ramping or tracking foldback output current limiting output overvoltage protection power good output voltage monitor 28-pin 4mm 4mm qfn and narrow ssop packages notebook and palmtop computers portable instruments battery-operated digital devices dc power distribution systems , lt, ltc, ltm, burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. 0.1 f 63.4k 2.2 h 2.2k 220pf 0.1 f 0.1 f 4.7 f 22 f 50v 100 f 6v 20k 15k v out1 3.3v 5a 0.1 f 43.2k 2.2 h 220pf 10nf 100 f 6v 20k 15k 10k v out2 2.5v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq/pllfltr sense1 + sense2 + run2 sense1 sense2 v fb1 v fb2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 24v 3850 ta01 0.1 f 0.1 f ltc3850 mode/pllin i lim run1 500khz 2.2k ef? ciency load current (ma) 10 70 efficiency (%) power loss (mw) 75 80 85 90 100 1000 10000 65 60 55 50 95 100 100 1000 10 10000 3850 ta01b power loss efficiency v in = 12v v out = 3.3v
ltc3850 2 3850f package/order information absolute maximum ratings input supply voltage (v in ) ......................... 28v to C 0.3v top side driver voltages (boost1, boost2) ............................... 34v to C 0.3v switch voltage (sw1, sw2) ......................... 28v to C 5v intv cc , run1, run2, pgood, extv cc , (boost1-sw1), (boost2-sw2) ............. 6v to C 0.3v sense1 + , sense2 + , sense1 C , sense2 C voltages ................................ 5.5v to C 0.3v mode/pllin, i lim ,tk/ss1,tk/ss2, freq/pllfltr voltages ............................................intv cc to C 0.3v (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead narrow plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run1 sense1 + sense1 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 sense2 + run2 i lim freq/pllfltr mode/pllin sw1 tg1 boost1 bg1 v in intv cc bg2 pgnd boost2 tg2 sw2 pgood t jmax = 125c, ja = 95c/w 28 27 26 25 24 23 8 9 top view 29 uf package 28-lead (4mm 4mm) plastic qfn 10 11 12 13 14 tk/ss1 i th1 v fb1 v fb2 i th2 tk/ss2 sense2 boost1 bg1 v in intv cc bg2 pgnd boost2 sense1 sense1 + run1 freq/pllfltr mode/pllin sw1 tg1 sense2 + run2 i lim extv cc pgood sw2 tg2 16 15 17 18 19 20 21 6 7 5 4 3 2 1 22 t jmax = 125c, ja = 37c/w, jc = 2.6c/w exposed pad (pin 29) is gnd, must be soldered to pcb order part number order part number uf part marking LTC3850EGN ltc3850euf 3850 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. i th1 , i th2 , v fb1 , v fb2 voltages .................. 2.7v to C 0.3v intv cc peak output current ................................100ma operating temperature range (note 2) ltc3850e ............................................C 40c to 85c junction temperature (note 3) ............................. 125c storage temperature range ...................C65c to 125c lead temperature (soldering, 10 sec) (gn package) .................................................... 300c
ltc3850 3 3850f electrical characteristics symbol parameter conditions min typ max units main control loops v fb1,2 regulated feedback voltage i th1,2 voltage = 1.2v; (note 4) 0.792 0.800 0.808 v i fb1,2 feedback current (note 4) C10 C50 na v reflnreg reference voltage line regulation v in = 6v to 24v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; 6 i th voltage = 1.2v to 0.7v measured in servo loop; 6 i th voltage = 1.2v to 1.6v 0.01 C0.01 0.1 C0.1 % % g m1,2 transconductance ampli? er g m i th1,2 = 1.2v; sink/source 5a; (note 4) 2.2 mmho i q input dc supply current normal mode shutdown (note 5) v in = 15v; extv cc tied to v out1 ; v out1 = 5v v run1,2 = 0v 850 30 50 a a uvlo undervoltage lockout on intv cc v intvcc ramping down 3 v uvlo hys uvlo hysteresis 0.5 v df max maximum duty factor in dropout 96 97.2 % v ovl feedback overvoltage lockout measured at v fb1,2 0.84 0.86 0.88 v i sense sense pins total current (each channel) v sense1,2 = 3.3v 1 2 a i tk/ss1,2 soft-start charge current v tk/ss1,2 = 0v 0.9 1.3 1.7 a v run1,2 run pin on threshold v run1 , v run2 rising 1.1 1.22 1.35 v v run1,2hys run pin on hysteresis 80 mv v sense(max) maximum current sense threshold v fb1,2 = 0.7v, v sense1,2 = 3.3v, i lim = 0v v fb1,2 = 0.7v, v sense1,2 = 3.3v, i lim = float v fb1,2 = 0.7v, v sense1,2 = 3.3v, i lim = intv cc 20 40 60 30 50 75 40 60 90 mv mv mv tg r up tg driver pull-up on-resistance tg high 2.6 1 tg r down tg driver pulldown on-resistance tg low 1.5 1 bg r up bg driver pull-up on-resistance bg high 2.4 1 bg r down bg driver pulldown on-resistance bg low 1.1 1 tg1,2 t r tg1,2 t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg1,2 t r bg1,2 t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 7v < v in < 24v 4.8 5 5.2 v v ldo int intv cc load regulation i cc = 0ma to 50ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 50 100 mv the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v in = 15v, v run1,2 = 5v, unless otherwise noted.
ltc3850 4 3850f input voltage (v) 5 80 efficiency (%) power loss (mw) 90 100 95 10 15 85 0 1000 2000 500 1500 20 25 3850 g03 power loss efficiency circuit of figure 12 v out = 3.3v i out = 2a load current (ma) circuit of figure 12 10 40 efficiency (%) 50 60 70 80 100 1000 10000 30 20 10 0 90 100 3850 g01 burst dcm ccm v in = 12v v out = 1.8v load current (ma) 10 40 efficiency (%) 50 60 70 80 100 1000 10000 30 20 10 0 90 100 3850 g02 burst dcm ccm circuit of figure 12 v in = 12v v out = 3.3v ef? ciency vs output current and mode ef? ciency and power loss vs input voltage electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3850e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: LTC3850EGN: t j = t a + (p d ? 95c/w) ltc3850euf: t j = t a + (p d ? 37c/w) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v in = 15v, v run1,2 = 5v, unless otherwise noted. symbol parameter conditions min typ max units v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0v 210 250 290 khz f high highest frequency v freq 2.4v 700 780 860 khz r mode/pllin mode/pllin input resistance 250 k 1 i freq phase detector output current sinking capability sourcing capability f mode < f osc f mode > f osc C13 13 a a pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative v fb ramping positive C5 5 C 7.5 7.5 C10 10 % % note 4: the ltc3850 is tested in a feedback loop that servos v ith1,2 to a speci? ed voltage and measures the resultant v fb1,2 . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is speci? ed for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). typical application ef? ciency vs output current and mode
ltc3850 5 3850f typical performance characteristics load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load coincident tracking prebiased output at 2v 40 s/div v out 100mv/div ac coupled i l 2a/div i load 2a/div 200ma to 2.5a 3850 g04 circuit of figure 12 v in = 12v, v out = 1.8v 40 s/div circuit of figure 12 v in = 12v, v out = 1.8v i l 2a/div i load 2a/div 200ma to 2.5a v out 100mv/div ac coupled 3850 g05 40 s/div i l 2a/div i load 2a/div 200ma to 2.5a v out 100mv/div ac coupled 3850 g06 circuit of figure 12 v in = 12v, v out = 1.8v 1ms/div run1 2v/div v out1 , 3.3v 3 ? load, 1v/div v out2 , 1.8v 1.5 ? load 1v/div 3850 g09 1 s/div burst mode operation 2a/div forced continuous mode 2a/div pulse-skipping mode 2a/div 3850 g07 circuit of figure 12 v in = 12v, v out = 1.8v i load = 100 a 2.5ms/div v out 2v/div v fb 500mv/div 3850 g08 v tk/ss 500mv/div
ltc3850 6 3850f feedback voltage (v) 0 maximum current sense voltage (mv) 40 50 60 0.8 3850 g16 30 20 0 0.2 0.4 0.6 0.1 0.9 0.3 0.5 0.7 10 80 70 i lim = intv cc i lim = float i lim = gnd temperature ( c) ?0 2.00 1.75 1.50 1.25 1.00 25 75 3850 g17 ?5 0 50 100 tk/ss current ( a) v ith (v) 0 ?0 v sense (mv) ?0 0 20 40 60 80 0.5 1 1.5 2 3850 g13 i lim = intv cc i lim = gnd i lim = float v sense common mode voltage (v) 0 current sense threshold (mv) 30 40 50 3 5 20 10 0 12 4 60 70 80 3850 g14 i lim = intv cc i lim = gnd i lim = float 60 80 100 40 20 50 70 90 30 10 0 duty cycle (%) 0 current sense threshold (mv) 60 100 20 40 80 3850 g15 i lim = intv cc i lim = gnd i lim = float input voltage (v) intv cc voltage (v) 3850 g12 4.75 5.00 5.25 4.50 4.25 4.00 3.75 3.50 020 51015 25 input voltage (v) 5 supply current (ma) 2 3 25 3850 g11 1 0 10 15 20 5 4 typical performance characteristics quiescent current vs input voltage without extv cc intv cc line regulation current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs duty cycle maximum current sense voltage vs feedback voltage (current foldback) tk/ss pull-up current vs temperature tracking up and down with external ramp 10ms/div v out1 3.3v 3 ? load 1v/div v out2 1.8v 1.5 ? load 1v/div tk/ss1 tk/ss2 2v/div 3850 g10
ltc3850 7 3850f temperature ( c) ?0 1.5 1.4 1.3 1.2 1.1 1.0 25 75 3850 g18 ?5 0 50 100 run pin voltage (v) on off temperature ( c) ?0 806 804 802 800 798 796 794 25 75 3850 g19 ?5 0 50 100 regulated feedback voltage (mv) temperature ( c) ?0 900 800 700 600 500 400 300 200 25 75 3850 g20 ?5 0 50 100 frequency (khz) v freq = intv cc v freq = 1.2v v freq = 0v temperature ( c) ?0 5 4 3 2 1 0 25 75 3850 g21 ?5 0 50 100 intv cc voltage (v) rising falling input voltage (v) frequency (khz) 3850 g22 420 410 400 390 380 5 10 15 20 25 input voltage (v) input current ( a) 3850 g23 50 40 30 20 10 0 5 10 15 20 25 temperature ( c) ?0 50 40 30 20 10 0 25 75 3850 g24 ?5 0 50 100 shutdown current ( a) v in = 15v temperature ( c) ?0 5 4 3 2 1 0 25 75 3850 g25 ?5 0 50 100 quiescent current (ma) typical performance characteristics shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage shutdown current vs temperature quiescent current vs temperature without extv cc shutdown current vs input voltage
ltc3850 8 3850f pin functions run1, run2 (pins 1, 13/pins 26, 9): run control inputs. a voltage above 1.2v on either pin turns on the ic. how- ever, forcing either of these pins below 1.2v causes the ic to shut down that particular channel. there are 0.5a pull-up currents for these pins. once the run pin rises above 1.2v, an additional 4.5a pull-up current is added to the pin. sense1 + , sense2 + (pins 2, 12/pins 27, 8): current sense comparator inputs. the (+) inputs to the current comparators are normally connected to dcr sensing networks or current sensing resistors. sense1 C , sense2 C (pins 3, 11/pins 28, 7): current sense comparator inputs. the (C) inputs to the current comparators are connected to the outputs. tk/ss1, tk/ss2 (pins 4, 10/pins 1, 6): output voltage tracking and soft-start inputs. when one channel is con? gured to be master of the two channels, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is con? gured to be the slave of two channels, the v fb voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft-start currents of 1.3a charge the soft-start capacitors. i th1 , i th2 (pins 5, 9/pins 2, 5): current control thresholds and error ampli? er compensation points. each associated channels current comparator tripping threshold increases with its i th control voltage. v fb1 , v fb2 (pins 6, 8/pins 3, 4): error ampli? er feedback inputs. these pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. sgnd (pin 7/pin 29): signal ground. all small-signal components and compensation components should con- nect to this ground, which in turn connects to pgnd at one point. pin 29 is the exposed pad, only available on the uf package. extv cc (na/pin 11): external power input to an internal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7v. do not exceed 6v on this pin. i lim (pin 14/pin 10): current comparator sense voltage range inputs. tying this pin to sgnd, float or intv cc sets the maximum current sense threshold to three dif- ferent levels for each comparator. pgood (pin 15/pin 12): power good indicator output. open-drain logic out that is pulled to ground when either channel output exceeds the 7.5% regulation window, after the internal 17s power bad mask timer expires. pgnd (pin 19/pin 16): power ground pin. connect this pin closely to the sources of the bottom n-channel mosfets, the (C) terminal of cv cc and the (C) terminal of c in . intv cc (pin 21/pin 18): internal 5v regulator output. the control circuits are powered from this voltage. decouple this pin to pgnd with a 4.7f low esr tantalum or ceramic capacitor. v in (pin 22/pin 19): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). bg1, bg2 (pins 23, 20/pins 20, 17): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mosfets and swings between pgnd and intv cc . boost1, boost2 (pins 24, 18/pins 21, 15): boosted floating driver supplies. the (+) terminal of the boost-strap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . tg1, tg2 (pins 25, 17/pins 22, 14): top gate driver outputs. these are the outputs of ? oating drivers with a voltage swing equal to intv cc superimposed on the switch nodes voltages. sw1, sw2 (pins 26, 16/pins 23, 13): switch node con- nections to inductors. voltage swing at these pins are from a body diode voltage drop below ground to v in . mode/pllin (pin 27/pin 24): force continuous mode, burst mode, or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force both channels into the continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leaving the pin ? oating will enable burst mode operation. a clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator. (gn/uf)
ltc3850 9 3850f pin functions freq/pllfltr (pin 28/pin 25): the phase-locked loops low-pass filter is tied to this pin. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. exposed pad (pin 29, uf package only): signal ground. must be soldered to pcb, providing a local ground for the control components of the ic, and be tied to the pgnd pin under the ic. functional diagram 4.7v + + + + v in 0.5 a slope compensation uvlo slope recovery active clamp osc s rq 3k run switch logic and anti- shoot through bg on fcnt 0.8v ov 1 51k 1.2v 0.64v i th r c intv cc intv cc i lim i thb i cmp c c1 ea ss sgnd r1 0.86v r2 run pgnd pgood intv cc extv cc i rev sw tg c b v in c in v in sleep boost bursten + + uv ov c vcc v out c out m2 m1 l1 d b mode/pllin sense + sense + 0.8v ref tk/ss run 0.55v + v fb freq/pllfltr pll-sync mode/sync detect + + 5v reg 1.3 a c ss + + + f f 0.74v 3850 fd
ltc3850 10 3850f operation main control loop the ltc3850 is a constant-frequency, current mode step- down controller with two channels operating 180 degrees out-of-phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error ampli- ? er ea. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator i rev , or the beginning of the next cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, an internal 5v low dropout linear regula- tor supplies intv cc power from v in . if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc . using the extv cc pin allows the intv cc power to be derived from a high ef? ciency external source such as one of the ltc3850 switching regulator outputs. each top mosfet driver is biased from the ? oating boot- strap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period every third cycle to allow c b to recharge. however, it is recommended that a load be present during the drop-out transition to ensure c b is recharged. shutdown and start-up (run1, run2 and tk/ss1, tk/ss2 pins) the two channels of the ltc3850 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.2v shuts down the main control loop for that controller. pulling both pins low disables both controllers and most internal circuits, including the intv cc regulator. releasing either run pin allows an internal 0.5a current to pull up the pin and enable that control- ler. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of each controllers output voltage v out is controlled by the voltage on the tk/ss1 and tk/ss2 pins. when the voltage on the tk/ss pin is less than the 0.8v internal reference, the ltc3850 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.8v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.3a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.8v (and beyond), the output voltage v out rises smoothly from zero to its ? nal value. alternatively the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground (see the applica- tions information section). when the corresponding run pin is pulled low to disable a controller, or when intv cc drops below its undervoltage lockout threshold of 3v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, both controllers are disabled and the external mosfets are held off. light load current operation (burst mode operation, pulse-skipping, or continuous conduction) the ltc3850 can be enabled to enter high ef? ciency burst mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.8v (e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, ? oat the mode/pllin pin.
ltc3850 11 3850f when a controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error ampli? er ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from revers- ing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur- rent is determined by the voltage on the i th pin, just as in normal operation. in this mode, the ef? ciency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the ltc3850 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current ef? ciency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq/pllfltr and mode/pllin pins) the selection of switching frequency is a trade-off between ef? ciency and component size. low frequency operation increases ef? ciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main- tain low output ripple voltage. the switching frequency of the ltc3850s controllers can be selected using the freq/pllfltr pin. if the mode/pllin pin is not being driven by an external clock source, the freq/pllfltr pin can be used to program the controllers operating frequency from 250khz to 780khz. a phase-locked loop (pll) is available on the ltc3850 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. a series r-c should be connected between the freq/pllfltr pin and sgnd to serve as the plls loop ? lter. power good (pgood pin) the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when either v fb pin voltage is not within 7.5% of the 0.8v reference voltage. the pgood pin is also pulled low when either run pin is below 1.2v or when the ltc3850 is in the soft-start or tracking phase. when the v fb pin voltage is within the 7.5% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will ? ag power good immediately when both v fb pins are within the 7.5% window. however, there is an internal 17s power bad mask when either v fb goes out of the 7.5% window. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (> 7.5%) as well as other more serious con- ditions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. operation
ltc3850 12 3850f the typical application on the ? rst page is a basic ltc3850 application circuit. ltc3850 can be con? gured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resis- tors and is more power ef? cient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load require- ment, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maximum current limit of the controller. when i lim is grounded, the maximum current limit threshold of the current compara- tor is programmed to be 30mv. when i lim is ? oated, the maximum current limit threshold is 50mv. when i lim is tied to intv cc , the maximum current limit threshold is set to 75mv. applications information sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 5v. both sense pins are high impedance inputs with small base currents of less than 1a. when the sense pins ramp up from 0v to 1.4v, the small base currents ? ow out of the sense pins. when the sense pins ramp down from 5v to 1.1v, the small base currents ? ow into the sense pins. the high impedance inputs to the current comparators allow accurate dcr sensing. however, care must be taken not to ? oat these pins during normal operation. filter components mutual to the sense lines should be placed close to the ltc3850, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur- rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. figure 2. two different methods of sensing current v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins sense + sense sgnd ltc3850 v out 3850 f02a figure 1. sense lines placement with inductor or sense resistor v in v in intv cc boost tg sw bg pgnd *place c1 near sense + , sense pins inductor dcr l sense + sense sgnd ltc3850 v out 3850 f02b r1 r2 c1* r1 || r2 c1 = l dcr r sense(eq) = dcr r2 r1 + r2 c out to sense filter, next to the controller inductor or r sense 3850 f01 (2a) using a resistor to sense current (2b) using the inductor dcr to sense current
ltc3850 13 3850f low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the input common mode range of the current comparator is 0v to 5v. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to- peak ripple current, i l . to calculate the sense resistor value, use the equation: r v i i sense sense max max l = + () () ? 2 inductor dcr sensing for applications requiring the highest possible ef? ciency at high load currents, the ltc3850 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost sev- eral points of ef? ciency compared to dcr sensing. if the external r1 || r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external ? lter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers datasheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r v i i sense equiv sense max max l () () () = + ? 2 to ensure that the application will deliver full load cur- rent over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (20mv, 40mv, or 60mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the tempera- ture coef? cient of resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r r dcr at t d sense equiv max l max = () () () c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1 || r2 to around 2k , reducing error that might have been caused by the sense pins 1a current. the equivalent resistance r1 || r2 is scaled to the room temperature inductance and maximum dcr: rr l dcr at c c 12 20 1 || () = the sense resistor values are: r rr r r rr r d d d 1 12 2 1 1 == ? || ; the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: pr vvv r loss in max out out 1 1 = ? () () ensure that r1 has a power rating higher than this value. if high ef? ciency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. applications information
ltc3850 14 3850f however, dcr sensing eliminates a sense resistor, re- duces conduction losses and provides higher ef? ciency at heavy loads. peak ef? ciency is about the same with either method. slope compensation and inductor peak current slope compensation provides stability in constant- frequency architectures by preventing subharmonic oscillations at high duty cycles. it is accomplished inter- nally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak cur- rent for duty cycles > 40%. however, the ltc3850 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i v v vv fl ripple out in in out osc = ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest ef? ciency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a speci? ed maximum, the inductor should be chosen according to: l vv fi v v in out osc ripple out in inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a ? xed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfets must be selected for each controller in the ltc3850: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss speci? cation for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately ? at divided by the speci? ed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve speci? ed v ds . when the ic is applications information
ltc3850 15 3850f operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switc out in = h h duty cycle vv v in out in = the mosfet power dissipations at maximum output current are given by: p v v ir v i main out in max ds on in max = () + () + () 2 2 1 () 22 11 ? ? ? ? ? ? ()( ) + rc vv v dr miller intvcc th min () t th min sync in out in max f p vv v i () ? ? ? ? ? ? ? ? ( ) = () 2 11 + () r ds on () where is the temperature dependency of r ds(on) and r dr (approximately 2 ) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current ef? ciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher ef? ciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diodes shown on the ? rst page conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in ef? ciency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. soft-start and tracking the ltc3850 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is con? gured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2v. its tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.2v, the channel powers up. a soft-start current of 1.3a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is de? ned to be the voltage range from 0v to 0.8v on the tk/ss pin. the total soft-start time can be calculated as: t c a softstart ss = 08 13 . . regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.64v. between tk/ss = 0.64v and 0.74v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.74v. the output ripple is minimized during the 100mv forced continuous mode window ensuring a clean pgood signal. when the channel is con? gured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, applications information
ltc3850 16 3850f figure 5. equivalent input circuit of error ampli? er + ii d1 tk/ss2 0.8v v fb2 d2 d3 3850 f05 ea2 time (3a) coincident tracking v out1 v out2 output voltage 3850 f03a v out1 v out2 time 3850 f03b (3b) ratiometric tracking output voltage figure 3. two different modes of output voltage tracking r3 r1 r4 r2 r3 v out2 r4 (4a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3850 f04 (4b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 figure 4. setup for coincident and ratiometric tracking applications information
ltc3850 17 3850f the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always ? owing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the ltc3850 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.74v regardless of the setting on the mode/pllin pin. however, the ltc3850 should always be set in force continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, its channel will operate in discontinuous mode. output voltage tracking the ltc3850 allows the user to program how its out- put ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to ei- ther coincidentally or ratiometrically track another supplys output, as shown in figure 3. in the following discussions, v out1 refers to the ltc3850s output 1 as a master channel and v out2 refers to the ltc3850s output 2 as a slave channel. to implement the coincident track- ing in figure 3a, connect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 4a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking, the ratio of the v out2 divider should be exactly the same as the master channels feedback divider. by selecting differ- ent resistors, the ltc3850 can achieve different modes of tracking including the two in figure 3. so which mode should be programmed? while either mode in figure 4 satis? es most practical applications, some tradeoffs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. this can be better understood with the help of figure 5. at the input stage of the slave channels error ampli? er, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the coincident mode, the tk/ss voltage is substantially higher than 0.8v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal precision 0.8v reference. in the ratiometric mode, however, tk/ss equals 0.8v at steady state. d1 will divert part of the bias current to make v fb2 slightly lower than 0.8v. although this error is minimized by the exponential i-v characteristic of the diode, it does impose a ? nite amount of output voltage deviation. furthermore, when the master channels output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. intv cc regulators and extv cc the ltc3850 features an npn low dropout linear regulator (ldo) that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the ltc3850s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5v when v in is greater than 6.5v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v. each of these can supply a peak current of 100ma and must be bypassed to ground with a minimum of 1f ceramic capacitor or low esr electrolytic capacitor. no mat- ter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3850 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5v ldo or extv cc . when the voltage on the extv cc pin is less than 4.7v, the ldo is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the ef? ciency considerations section. the junction temperature can be estimated by using the equa- tions given in note 3 of the electrical characteristics. for applications information
ltc3850 18 3850f example, the ltc3850 intv cc current is limited to less than 24ma from a 24v supply in the gn package and not using the extv cc supply: t j = 70c + (24ma)(24v)(95c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (mode/pllin = sgnd) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the intv cc ldo is turned off and the extv cc is connected to the intv cc . the extv cc re- mains on as long as the voltage applied to extv cc remains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from one of the ltc3850s switching regulator outputs during normal operation and from the intv cc when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc than is speci? ed, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc < v in . signi? cant ef? ciency and thermal gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher ef? ciency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (24ma)(5v)(95c/w) = 81c however, for 3.3v and other low voltage outputs, addi- tional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an ef? ciency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest ef? ciency. 3. extv cc connected to an external supply. if a 5v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, ef? ciency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with the capacitive charge pump shown in figure 6. applications information figure 6. capacitive charge pump for extv cc extv cc v in tg1 sw bg1 pgnd ltc3850 r sense v out vn2222ll + c out 3850 f06 n-ch n-ch + c in 1 f v in l1 bat85 bat85 bat85 0.22 f topside mosfet driver supply (c b , db) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode db from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capa- citance of the topside mosfet(s). the reverse break- down of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the ? nal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the ef? ciency has improved. if there is no change in input current, then there is no change in ef? ciency.
ltc3850 19 3850f undervoltage lockout the ltc3850 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 500mv of precision hysteresis. another way to detect an undervoltage condition is to monitor the v in supply. because the run pins have a precision turn-on reference of 1.2v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5a of current ? ows out of the run pin once the run pin voltage passes 1.2v. one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. c in and c out selection the selection of c in is simpli? ed by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of- phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c quired i i v vvv in rms max in out in out re ()( ) ? ? ? ?? 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3850, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the bene? t of the ltc3850 2-phase operation can be cal- culated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both control- lers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall bene? t of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the ef? ciency testing. the sources of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3850, is also suggested. a 10 resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple ( v out ) is approximated by: ? + ? ? ? ? ? ? vi esr fc out ripple out 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. applications information
ltc3850 20 3850f setting output voltage the ltc3850 output voltages are each set by an external feedback resistive divider carefully placed across the output, as shown in figure 7. the regulated output volt- age is determined by: vv r r out b a =+ ? ? ? ? ? ? 08 1 . to improve the frequency response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on- time t on(min) of the ltc3850 ( 90ns), the input voltage and inductor value: ? it v l lsc onmin in () ( ) = the resulting short-circuit current is: i v r i sc sense max sense lsc = 13 1 2 / () () ? phase-locked loop and frequency synchronization the ltc3850 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (v co ) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the turn-on of controller 2s top mosfet is thus 180 degrees out- of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the external ? lter network connected to the freq/pllfltr pin. the fault conditions: current limit and current foldback the ltc3850 includes current foldback to help limit load current when the output is shorted to ground. if the out- put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions with very low duty cycles, the ltc3850 will begin cycle freq/pllfltr pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3850 f08 2.5 0 100 300 400 500 900 800 700 200 600 1/2 ltc3850 v fb v out r b c ff r a 3850 f07 figure 8. relationship between oscillator frequency and voltage at the freq/pllfltr pin figure 7. setting output voltage applications information
ltc3850 21 3850f relationship between the voltage on the freq/pllfltr pin and operating frequency is shown in figure 8 and speci? ed in the electrical characteristics table. note that the ltc3850 can only be synchronized to an external clock whose frequency is within range of the ltc3850s internal v co . this is guaranteed to be between 250khz and 780khz. a simpli? ed block diagram is shown in figure 9. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the freq/pllfltr pin. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the freq/pllfltr pin. if the external and internal frequen- cies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the freq/pllfltr pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the ? lter capacitor c lp holds the voltage. the loop ? lter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the ? lter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01f. typically, the external clock (on mode/pllin pin) input high threshold is 1.6v, while the input low thres- hold is 1.2v. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc3850 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t v v on min out in () () < f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3850 is approximately 90ns. however, as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signi? cant amount of cycle skipping can occur with cor- respondingly larger current and voltage ripple. digital phase/ frequency detector vco 2.4v r lp c lp 3850 f09 freq/ pllfltr external oscillator mode/ pllin figure 9. phase-locked loop block diagram applications information
ltc3850 22 3850f ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: %ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3850 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi- cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an out- put-derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(ef? ciency). for example, in a 20v to 5v applica- tion, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor. in continuous mode, the average output current ? ows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 10m , r l = 10m , r sense = 5m , then the total resistance is 25m . this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. ef? ciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become signi? cant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% ef? ciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. the ltc3850 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. applications information
ltc3850 23 3850f checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac ? ltered closed loop response test point. the dc step, rise time and settling at this test point truly re? ects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c ? lter sets the dominant pole-zero loop compensation. the values can be modi? ed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break- ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the ? ltered and compensated control loop response. the gain of the loop will be in- creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. applications information
ltc3850 24 3850f pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 10. figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1 cm of each other with a common drain con- nection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter- minals. the v fb and i th traces should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3850 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal applications information c b2 c b1 c intvcc + c in d1 1 f ceramic m1 m2 m3 m4 d2 + c vin v in r in l1 l2 c out1 v out1 gnd v out2 3850 f10 + c out2 + r sense r sense r pu2 pgood v pull-up f in 1 f ceramic i th1 v fb1 sense1 + sense1 plllpf sense2 sense2 + v fb2 i th2 tk/ss2 tk/ss1 pgood tg1 sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 sgnd i lim mode/pllin run1 run2 figure 10. recommended printed circuit layout diagram
ltc3850 25 3850f ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense + and sense C leads routed together with minimum pc trace spacing? the ? lter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposite channels voltage and current sensing feed- back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3850 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 2b, r1) close to the switching node. 7. use a modi? ed star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. applications information r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3850 f11 r sense2 v out2 c out2 figure 11. branch current waveforms
ltc3850 26 3850f pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed cur- rent level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb imple- mentation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over- compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly dif? cult region of operation is when one controller channel is nearing its current com- parator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. design example as a design example for a two channel medium current regu- lator, assume v in = 12v(nominal), v in = 20v(maximum), v out1 = 3.3v, v out2 = 1.8v, i max1,2 = 5a, and f = 500khz (see figure 12). the regulated output voltages are determined by: vv r r out b a =+ ? ? ? ? ? ? 08 1 . using 20k 1% resistors from both v fb nodes to ground, the top feedback resistors are (to the nearest 1% standard value) 63.4k and 25.5k. the frequency is set by biasing the freq/pllfltr pin to 1.2v (see figure 8), using a divider from intv cc . this voltage will decrease as v in approaches 5v, lowering the switching frequency. if a separate 5v supply is connected to extv cc , intv cc will remain at 5v even if v in decreases. the inductance values are based on a 35% maximum ripple current assumption (1.75a for each channel). the highest value of ripple current occurs at the maximum input voltage: l v i v v out lmax out in max =? ? ? ? ? ? ? f () () ? 1 channel 1 will require 3.2h, and channel 2 will require 1.9h. the next highest standard values are 3.3h and 2.2h. at the nominal input voltage (12v), the ripple will be: ? i v l v v l nom out out in nom () () =? ? ? ? ? ? ? f 1 channel 1 will have 1.45a (29%) ripple, and channel 2 will have 1.4a (28%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 5.725a for channel 1 and 5.7a for channel 2. applications information
ltc3850 27 3850f the minimum on-time occurs on channel 1 at the maximum v in , and should not be less than 90ns: t v v v vkhz n on min out in max () () . () == = f 18 20 500 180 s s with i lim ? oating, the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (40mv). r v i i sense equiv sense min load max l nom () () () ( = + ? )) . 2 40 5 15 2 7 = + ? mv a a m ? the equivalent r sense is the same for channel 2. the coiltronics (cooper) hcp0703-2r2 (20m dcr max at 20c) and hcp0703-3r3 (30m dcr max at 20c) are chosen. at 100c, the estimated maximum dcr values are 26.4m and 39.6m . the divider ratios are: r r dcr at t m m d sense equiv max l max === () () . 7 26 4 0 ? ? .. ; . . 26 7 39 6 018 and m m ? ? ? for each channel, 0.1f is selected for c1. rr l dcr at c c h mf max 12 20 1 22 20 0 1 1 || () . ? = = = ? .. ; . ? . 1 33 30 0 1 11 kand h mf k ? = for channel 1, the dcr sense ? lter/divider values are: r rr r k k r rr r d d d 1 12 11 018 619 2 1 1 61 ==? = ? = || . . .; ? 9 9018 1018 133 k k ? . . ? ? applications information figure 12. high ef? ciency dual 500khz 3.3v/1.8v step-down converter d3 d4 m1 0.1 f 63.4k 1% 3.3 h 4.12k 1% 1800pf 100pf 0.1 f 0.1 f 22 f 50v c out1 100 f x2 l1, l2: coiltronics hcp0703 m1, m2: vishay siliconix si4816bdy c out1 , c out2 : taiyo yuden jmk325bj107mm 20k 1% 4.75k 1% v out1 3.3v 5a m2 0.1 f 25.5k 1% 2.2 h 1.5k 1% 2200pf 100pf c out2 100 f x2 20k 1% 5.49k 1% 3.16k 1% v out2 1.8v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq/pllfltr sense1 + sense2 + run2 sense1 sense2 v fb1 v fb2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 20v 3850 f12 extv cc 0.1 f 0.1 f ltc3850euf mode/pllin i lim run1 6.19k 1% 1.33k 1% 10k, 1% 4.7 f 33pf 33pf
ltc3850 28 3850f the power loss in r1 at the maximum input voltage is: pr vvv r vv loss in max out out 1 1 20 3 3 3 = ? = ? () (.) () .. . 3 619 9 v k mw = the respective values for channel 2 are r1 = 4.12k, r2 = 1.5k; and p loss r1 = 8mw. burst mode operation is chosen for high light load ef? ciency (figure 13) by ? oating the mode/pllin pin. power loss due to the dcr sensing network is slightly higher at light loads than would have been the case with a suitable sense resistor (7m ). at heavier loads, dcr sensing provides higher ef? ciency. the power dissipation on the topside mosfet can be easily estimated. choosing a siliconix si4816bdy dual mosfet results in: r ds(on) = 0.023 /0.016 , c miller ? 100pf. at maximum input voltage with t(estimated) = 50c: p v v cc main = () + [] 33 20 5 1 0 005 50 25 00 2 . (. )( ) . 2 23 20 5 2 2 100 1 523 1 2 2 ? () + () ? ? ? ? ? ? ? ()( ) + v a pf ? .. 3 500 186 ? ? ? ? ? ? () = khz mw a short-circuit to ground will result in a folded back cur- rent of: i mv ns v h sc = () ? ? ? ? ? ? ? = 1350 0 007 1 2 90 20 33 / . () . 2 21 .a with a typical value of r ds(on) and = (0.005/c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p vv v a m sync = ()( ) ? () = 20 3 3 20 2 1 1 125 0 016 66 2 ? ... ww which is less than under full-load conditions. c in is chosen for an rms current rating of at least 2a at temperature assuming only channel 1 or 2 is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( i l ) = 0.02 (1.5a) = 30mv pCp figure 13. design example ef? ciency vs load applications information load current (ma) 0.01 70 efficiency (%) power loss (mw) 80 90 0.1 1 10 60 50 40 100 0.1 1 0.01 10 3850 f13 efficiency power loss dcr 7m ? dcr
ltc3850 29 3850f 2.5v/15a, 1.8v/15a with dcr sensing f sw = 400khz typical applications c4 0.22 f tk/ss1 i th1 v fb1 v fb2 i th2 tk/ss2 sense2 boost1 bg1 v in intv cc bg2 pgnd boost2 sense1 + run1 freq/ pllfltr mode/ pllin sw1 tg1 sense1 ? sense2 + run2 sgnd i lim sw2 tg2 extv cc pgood pgood m4 rjk0301- dpb d2 b34ola m3 hat2168h r27 1.91k r1 43.2k rv in 2.2 ? 9.31k c ss1 0.1 f c6 100pf c7 1000pf c b1 0.1 f d3 cmdsh-3 m2 rjk0301- dpb m1 hat2168h d1 b34ola d4 cmdsh-3 cv cc 4.7 f cv in 1 f c b2 0.1 f c10 33pf l1 0.68 h 330 f 4v 2x c in 180 f v out1 2.5v/ 15a v out2 1.8v/ 15a c5 0.22 f r pg 100k l1, l2: sumida cdep125me-or7mc c out1 , c out2 : sanyo 4tpd330m * for v in = 5v 0.5v, tie v in and intv cc pins together. r2 20k r12 7.5k r3 20k c15 47pf r4 25.5k c11 1000pf r18 4.99k c12 100pf c ss2 0.1 f v in * 7v to 14v pgnd gnd ltc3850euh 3850 ta02 r5 2.55k r11 10k r30 1.91k l2 0.68 h + 330 f 4v 2x + + 9.31k
ltc3850 30 3850f typical applications 2.5v/15a, 1.8v/15a synchronized at 400khz c4 1000pf c2 0.01 f tk/ss1 i th1 v fb1 v fb2 i th2 tk/ss2 sense2 boost1 bg1 v in intv cc bg2 pgnd boost2 sense1 + run1 freq/ pllfltr mode/ pllin sw1 tg1 sense1 ? pgood c1 1000pf m4 rjk0301dpb d2 b34ola m3 rjk0305dpb l2 0.68 h r sense1 0.003 ? r sense2 0.003 ? r9 10 ? r10 10 ? r5 10k pllin 400khz r1 43.2k rv in 2.2 ? c ss1 0.1 f c6 100pf c7 1000pf c b1 0.1 f d3 cmdsh-3 m2 rjk0301dpb m1 rjk0305dpb d1 b34ola d4 cmdsh-3 cv cc 4.7 f cv in 1 f c b2 0.1 f r20 10 ? c10 33pf l1 0.68 h v out1 2.5v/15a v out2 1.8v/15a c5 1000pf r22 10 ? rpg 100k r2 20k r12 7.5k r3 20k c15 47pf r4 25.5k c11 1000pf r18 4.99k c12 100pf c ss2 0.1 f ltc3850 3850 ta03 sense2 + run2 sgnd i lim sw2 tg2 extv cc pgood l1, l2: sumida cep125-or6mc c out1 , c out2 : sanyo 4tpd330m * for v in = 5v 0.5v, tie v in and intv cc pins together. pgnd gnd c in 180 f v in * 7v to 14v 330 f 4v 2x + 330 f 4v 2x + +
ltc3850 31 3850f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) package description 4.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.05 28 27 1 2 bottom view?xposed pad 2.64 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.20 0.05 0.40 bsc 0.200 ref 0.00 ?0.05 (uf28) qfn 0106 reva recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.20 0.05 0.40 bsc 2.64 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer r = 0.05 typ uf package 28-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1721 rev a) .386 ?.393* (9.804 ?9.982) gn28 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.19 ?0.25) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side
ltc3850 32 3850f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2007 lt 0607 ? printed in usa related parts typical application part number description comments ltc1625/ ltc1775 no r sense tm current mode synchronous step-down controllers 97% ef? ciency, no sense resistor, 16-pin ssop ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood ltc1735 high ef? ciency synchronous step-down switching regulator output fault protection, 16-pin ssop ltc1778 no r sense wide input range synchronous step-down controller up to 97% ef? ciency, 4v v in 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc3727a-1 dual, 2-phase synchronous controller very low dropout; v out 14v, 4v v in 36v ltc3728 2-phase 550khz, dual synchronous step-down controller qfn and ssop packages, high frequency for smaller l and c ltc3729 20a to 200a polyphase ? synchronous controllers expandable from 2-phase to 12-phase, uses all surface mount components ltc3731 3-phase, single output from 250khz to 600khz synchronous step-down controller 0.6v v out 6v, 4.5v v in 32v, i out 60a, integrated mosfet drivers ltc3773 triple output dc/dc synchronous controller 3-phase step-down dc/dc controller, 3.3v v in 36v, fixed frequency 160khz to 700khz ltc3827 low i q , dual, 2-phase synchronous step-down controller 80a i q , 0.8v v out 10v, 4v v in 36v ltc3828 dual, 2-phase synchronous step-down controller with tracking up to six phases, 0.8v v out 7v, 4.5v v in 28v ltc3835/ ltc3835-1 low i q , synchronous step-down controller 80a i q , 0.8v v out 10v, 4v v in 36v lt3845 low i q , high voltage single output synchronous step-down dc/dc controller 1.23v v out 36v, 4v v in 60v, 120a i q polyphase is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. c4 1000pf c2 0.01 f tk/ss1 i th1 v fb1 v fb2 i th2 tk/ss2 sense2 boost1 bg1 v in intv cc bg2 pgnd boost2 sense1 + run1 freq/ pllfltr mode/ pllin sw1 tg1 sense1 ? pgood c1 1000pf m4 rjk0301dpb d2 b34ola m3 hat2168h r9 10 ? r10 10 ? r5 10k pllin 750khz r1 63.4k rv in 2.2 ? c6 200pf c7 2000pf c b1 0.1 f d3 cmdsh-3 m2 rjk0301dpb m1 hat2168h d1 b34ola d4 cmdsh-3 cv cc 4.7 f cv in 0.1 f c b2 0.1 f r20 10 ? c10 33pf l1 0.68 h v out 3.3v/25a c5 1000pf r22 10 ? rpg 100k r2 20k r12 2.5k css 0.1 f ltc3850 3850 ta04 sense2 + run2 sgnd i lim sw2 tg2 extv cc pgood c out1 330 f 2x c out2 330 f 2x l1, l2: sumida cep125-or6mc c out1 , c out2 : sanyo 6tpd330m * for v in = 5v 0.5v, tie v in and intv cc pins together. pgnd gnd cv in2 180 f v in * 6v to 14v cv in1 180 f r sense1 0.003 ? r sense2 0.003 ? l2 0.68 h + + 3.3v/25a synchronized at 750khz

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